(1) Field of the Invention
The invention relates to the fabrication of integrated circuit devices, and more particularly, to a method and structure for the creation of a combined inductor and multiple capacitors structure.
(2) Description of the Prior Art
Developments in the semiconductor industry have over the years been aimed at creating higher performance devices for competitive or lower prices. These developments have resulted in extreme miniaturization of semiconductor devices that has been made possible by numerous and mutually supporting advances in semiconductor processes and by materials that are used for the creation of semiconductor devices, this in combination with new and sophisticated device designs. While most semiconductor devices are aimed at processing digital data, there has also been a broad stream of developments that is aimed at incorporating analog functions into circuits that process digital and analog data or analog data only. It is thereby the objective to create analog data processing devices using digital processing procedures and equipment. One of the major challenges in the creation of analog processing circuitry is that a number of the components that are used for analog circuitry are large in size and are therefore not readily integrated into digital devices that typically have feature sizes in the sub-micron range. The main components that offer a challenge in this respect are capacitors and inductors since both these components are, for typical analog processing circuit, of considerable size. The creation of inductive or capacitive components must therefore emphasize that these components can be created on a relatively small surface area of a semiconductor substrate while using methods and procedures that are well know in the art for the creation of semiconductor devices. The created inductor and capacitor must further be high quality components that can be used in high frequency applications while incurring minimum loss of power.
It is clear that, by combining the creation on one semiconductor monolithic substrate of circuitry that is aimed at the functions of digital and analog data manipulation and storage, a number of significant advantages are achieved. Such advantages include the reduction of manufacturing costs and the reduction of power consumption by the combined functions.
Capacitors and inductors are typically applied in the field of modern mobile communication applications that make use of compact high-frequency semiconductor devices. These devices have over the years continually improved in its performance characteristics, such as lower power consumption, smaller size of the device, wider frequency range of the applications, and lower noise levels. One of the main applications of semiconductor devices in the field of mobile communication is the creation of Radio Frequency (RF) amplifiers and oscillators. RF amplifiers or oscillators contain a number of standard components whereby however a major component of a typical RF amplifier is a tuned circuit that contains inductive and capacitive components. The electrical characteristic of a tuned circuit are such that, dependent on and determined by the magnitudes of its inductive and capacitive components, the tuned circuit forms an impedance that is frequency dependent, thereby enabling the tuned circuit to either be high or a low impedance for signals of a certain frequency. The tuned circuit can therefore either reject or pass and further amplify components of an analog signal based on the operating frequency range of that component. The tuned circuit can in this manner be used as a filter to filter out or remove signals of certain frequencies or to remove noise from a circuit configuration. One commonly used tuned circuit is the LC resonance circuit. One of the problems that is encountered when creating an inductor on the surface of a semiconductor substrate is that the self-resonance caused by the parasitic capacitance between the (spiral) inductor and the underlying substrate as well as the power consumption by parasitic resistances will limit the use of the inductor at high frequencies. As part of the design of such an inductor it is therefore of importance to reduce the capacitive coupling between the created inductor and the underlying substrate and resistive power loss.
Typically, inductors that are created on the surface of a substrate are of a spiral shape whereby the spiral is created in a plane that is parallel with the plane of the surface of the substrate. Conventional methods that are used to create the inductor on the surface of a substrate suffer several limitations. Most high quality factor (Q) inductors form part of a hybrid device configuration or of Monolithic Microwave Integrated Circuits (MMIC""s) are created as discrete components, the creation of which is not readily integratable into a typical process of Integrated Circuit manufacturing.
The parameter by which the applicability of an inductor is indicated is the Quality (Q) factor of the inductor. The quality factor Q of an inductor is defined as Q=Es/El, wherein Es is the energy that is stored in the reactive (i.e. inductive) portion of the component while El is the energy that is lost as heat in the resistive portion of the component. The higher the Q factor of the component, the closer the resistive value of the component approaches zero. For components, the quality factor serves as a measure of the purity of the reactance (or the susceptance) of the component, which can be degraded due to parasitics. In an actual configuration, there are always some physical resistors that will dissipate power, thereby decreasing the power that can be recovered. The quality factor Q is dimensionless. A Q value of greater than 100 is considered high enough for discrete inductors that are mounted on the surface of Printed Circuit Boards. For inductors that form part of an integrated circuit, the Q value is typically in the low range between about 3 and 20.
In creating an inductor on a monolithic substrate on which additional semiconductor devices are created, the parasitic capacitances that occur as part of this creation also limit the Q that can be achieved for the inductor to a value of 20 or less. This limitation, which is due to the smaller current flowing through the inductor as a consequence of the charging current of the parasitic capacitances, is for many applications not acceptable. Dependent on the frequency at which the LC circuit is designed to resonate, significantly larger values of Q, such as 100 or more, must be available. Prior Art has in this been limited to creating high values of Q as separate units, and in integrating these separate units with the surrounding device functions. This negates the advantages that can be obtained when using the monolithic construction of creating both the inductor and the surrounding devices on one and the same semiconductor substrate. The non-monolithic approach also has the disadvantage that additional wiring is required to interconnect the sub-components of the assembly, thereby again introducing additional parasitic capacitances and resistive losses over the interconnecting wiring network. For many of the applications of the RF amplifier, such as portable battery powered applications, power consumption is at a premium and must therefore be as low as possible. These problems take on even greater urgency with the rapid expansion of wireless applications such as portable telephones and the like. Wireless communications form a rapidly expanding market, where the integration of RF integrated circuits is one of the most important challenges. One of the approaches is to significantly increase the frequency of operation to for instance the range of 10 to 100 GHz. For such high frequencies, the value of the quality factor obtained from silicon-based inductors is significantly degraded. For applications in this frequency range, monolithic inductors have been created using sapphire or GaAs as a base. These inductors have a considerably lower parasitic capacitance and resistance than their counterparts using silicon technology and therefore provide higher frequencies of resonance of the LC circuit. Where more complex applications are required, the need still exists to create inductors using silicon as a substrate for lower cost solutions.
A number of different approaches have been used to incorporate inductors into a semiconductor environment without sacrificing device performance due to substrate losses. One of these approaches has used the selective removing (by etching) of the silicon underneath the inductor (using methods of micro-machining) thereby removing substrate parasitic effects. Another method has been to use multiple layers of metal (such as aluminum) interconnects or of copper damascene interconnects. Other applications use a high resistivity silicon substrate, thereby reducing resistive losses in the silicon substrate, since resistive losses in a substrate form a significant factor in determining the Q value of inductors. Biased wells have been proposed underneath a spiral conductor, this again aimed at reducing resistive losses in the surface of the substrate. All of these approaches have as common objectives to enhance the quality (Q) value of the inductor, to increase the frequency of the LC self-resonance thereby increasing the operating frequency range and to reduce the surface area for the creation of the inductor.
The above overview can be summarized as follows. Capacitors and inductors form valuable passive components that lend themselves to integration with active bipolar or MOS devices for analog functions in VLSI circuits. It is well known in the art that capacitors can be created between layers of polysilicon, poly to polycide or metal or between layers of metal. Capacitors can be either of a planar design, for reasons of process simplicity, or can be three dimensional resulting in a smaller footprint as commonly used in DRAM devices. Conventional implementations of integrated inductors can be of a spiral design that is implemented in a plane with the spiral containing one or more turns in the plane of the inductor or the integrated inductor can be of a multi-layered, metal design. Furthermore, an inductor can be of a solenoid design whereby the spacing between the layers of the solenoid is filled with a dielectric while the consecutive legs of the solenoid are interconnected by vias that are created in the dielectric. A multi-layered spiral inductor can extend as a spiral from the surface on which the inductor is created, the inductor that Is created in this manner can for instance be created containing three or more layers.
The previously stated considerations that relate to the design of an inductor can be summarized as follows. Integrated inductors should have a high value for Q while the inductive value must be maximized and the surface area over which the inductor is created must be minimized. Conventional CMOS technology limits the thickness of the metal that can be used for the creation of an inductor, thus limiting the desired reduction in resistive losses. The losses in the inductor are, as previously pointed out, further incurred by losses in the underlying substrate, which are caused by eddy currents (induced by current flowing in the inductor) in the silicon substrate and by current flowing through the inductor to parasitic capacitive components (that are created by the presence of the inductor over the surface of the substrate). Eddy currents can be minimized by increasing the isolation between the inductor and the substrate, by placing alternating regions of implanted n-well and p-well impurities in the silicon substrate underneath the inductor or by reverse biasing p-n junctions underneath the inductor. The energy loss that is incurred by the inductor to substrate capacitive coupling can be minimized by placing a ground shield between the inductor and the substrate, this ground shield can be further provided with holes, wedges; elongated openings (stripes) and the like for reduction of eddy currents that can occur in the ground shield. The solenoid shaped inductor offers the advantage that the eddy currents that are induced by this inductor are of lower value since the current that flows through this inductor essentially flows in a direction that is perpendicular to the surface of the underlying substrate.
The invention addresses the simultaneous creation of an inductor and multiple capacitors. The invention provides a method whereby multiple capacitors that are positioned in a vertical direction on the surface of the supporting substrate are created inside the legs (or inductor coils) of an inductor. In view of the fact that capacitors using silicon technology are typically created using materials that have weak magnetism, the presence of the capacitors inside the legs (or conductor coils) of the inductor will have only minimum effect on the magnetic field inside the inductor. This combination of capacitors that are located inside the legs of an inductor therefore results in significant savings of the surface area of the silicon substrate over which the components are created.
U.S. Pat. No. 5,416,356 (Staudinger et al.) shows a spiral inductor surrounded by a second plate of a capacitor.
U.S. Pat. No. 5,914,508 (Varmazis et al.) discloses a MMIC with an inductor.
U.S. Pat. No. 6,072,205 (Yamaguchi et al.), U.S. Pat. No. 5,352,998 (Tanino) and U.S. Pat. No. 5,481,131 (Staudinger et al.) show related devices.
J. Burghartz, xe2x80x9cIntegrated multilayer RF Passives in Silicon Technologyxe2x80x9d, Topical meetings on xe2x80x9cSilicon monolithic integrated Circuit in RF systemsxe2x80x9d, p. 141-147, 1998.
M. Stuber, M. Megahed, J. Lee, T. Kobayashi, and H. Domyo, xe2x80x9cSOI CMOS with high-performance passive components for analog, RF, and mixed-signal designxe2x80x9d. Proceedings 1998 IEEE International SOI Conference, p.99-100, 1998.
J. N. Burghartz, M. Soyuer, and K. Jenkins, xe2x80x9cIntegrated RF and Microwave components in BICMOS Technologyxe2x80x9d, IEEE Trans. on Electron Devices, V.43, No.9, p. 1559-1570, 1996.
S. Kamiyama, J. Drynan, Y. Takaishi, and K. Koyama, xe2x80x9cHighly reliable MIM capacitor technology using low pressure CVD-WN cylinder storage-node for 0.12 um-scale embedded DRAMxe2x80x9d, Symposium on VLSI Technology, paper #4A-4, p.39-40, 1999.
K. Kim, et al., xe2x80x9cA DRAM technology using MIM BST capacitor for 0.15 um DRAM generation and beyondxe2x80x9d, Symposium on VLSI Technology, paper #4A-1, p.33-34, 1999.
D. Edelstein and J. Burghartz, xe2x80x9cSpiral and solenoidal inductor structures on silicon using Cu-damascene interconnectsxe2x80x9d, IEEE International Interconnectsxe2x80x9d, Technology Conf., p. 1 8-20, 1998.
T. Lee, xe2x80x9cCMOS RF: no longer an oxymoronxe2x80x9d, p.244-247,1997.
C. Yue and S. Wong, xe2x80x9cA study on substrate effects of silicon-based RF passive componentsxe2x80x9d, IEEE MTT-S, Intl. Microwave Symposium, Vol. 4, p. 1625-1628, 1999.
J. Burghartz, xe2x80x9cProgress in RF inductors on siliconxe2x80x94understanding substrate lossesxe2x80x9d, 1998 Intl. Electron Device Meetings, p. 523-526, 1998.
A principle objective of the invention is to provide a method of creating multiple capacitors and an inductor with high Q value on the surface of a substrate whereby multiple capacitors are enclosed within the legs of the inductor.
Another objective of the invention is to simultaneously create multiple capacitors and an inductor on the surface of a substrate such that the surface area that is used for the creations of these multiple capacitors and an inductor is minimized.
In accordance with the objectives of the invention a new method and structure is provided for the simultaneous creation of inductive and capacitive components. The invention provides a method and structure whereby a vertical spiral inductor is created on the surface of a substrate. Multiple capacitors are created inside the coils of the vertical spiral conductor. A base layer of dielectric is deposited over the surface of a semiconductor substrate, contact plugs are provided in the base layer of dielectric. Multiple layers of dielectric are deposited over the surface of the base layer, layers of coils are created in the multiple layers of dielectric. Vias are provided in the layer of dielectric to interconnect overlying coils of the spiral inductor. An etch stop layer is deposited on the surface of the upper layer of dielectric. At least two openings are etched in the multiple layers of dielectric, these at least two openings are surrounded by the coils of the spiral inductor and align with the contact plugs provided in the base layers. Spacers are formed on the sidewalls of the openings, the bottom electrode layer, dielectric layer and top electrode layer of the at least two capacitors are deposited over the spacers. The openings are filled with a conductive material, the surface of the conductive material is polished down to the surface of the etch stop layer.